In the integrated circuit field, there are two types of circuits, the so-called conventional circuits and the so-called specific circuits, called ASICs. Manufacturers of conventional integrated circuits have standard circuit catalogs wherein the references each designate a particular standardized function. For specific applications, industrial users of integrated circuits prefer to have specific circuits developed, known as ASICs. When the term HDL or HDL-type model is used, it refers to a programming language for describing an integrated circuit that is considered to have a lower level relative to C++ language.
The various stages in the development of ASICs are the following:                definition of a functional specification,        modeling (defined below) of the ASIC in an HDL-type model description language and functional verification of the design associated with this modeling,        technological production by the integrated circuit manufacturer, and        hardware debugging of the circuit.        
Functional specification is defined as the generation of documents describing the functionalities covered by the ASIC.
It includes:                the system level specifications, describing:                    the functional visibility of the registers of the ASIC;            the coherence protocol that ensures the integrity of the data, in the case of a system with shared memory,            the specifications of the external interfaces of the components,                        and the specifications describing the choice of implementation of the ASIC.        
The HDL-type modeling of the ASIC consists in the description of Boolean logic equations that express its behavior in accordance with its specification. The HDL-type programming language used is a language dedicated to the description of the hardware objects of the integrated circuit (Hardware). It contains the primitives for describing the components with their interface signals as well as storage elements such as registers or memories.
The HDL-type description level serves as an entry point into the automatic generation process, resulting in the provision of masks for the technological processes for manufacturing the circuit.
The purpose of the functional verification of the design of the ASIC is to verify the compliance of the behavior of the HDL-type model of the ASIC with its functional specification before beginning the technological process.                Once the logic of the ASIC is stabilized, a quasi-automatic process applied to the HDL-type description of the ASIC makes it possible to generate a list of the physical cells constituting the ASIC and to generate the masks delivered to the foundry (ASIC manufacturer) for the manufacture of the circuit.        
The technological production of the circuit is the chemical process that makes it possible, using masks, to produce physical samples of the circuits.
Non-functional tests are applied after manufacturing to verify that the technological process has gone well and to select samples that are good candidates for mounting in packages for the next validation phase.
Hardware debugging is the first phase in the validation of ASICs in their real system environment after the samples are mounted in packages and connected to cards.
During the manufacturing stage, the ASIC manufacturer is unable to verify that the functional model of the ASIC provided by the industrial user does not include any design errors. It can only confirm the silicon chips compliance with the functional diagram requested.
One of the objects of the invention is to allow the industrial user of the ASIC, prior to the physical production of the circuit, to verify the exactitude of the functional model he is going to provide to the foundry (ASIC manufacturer).
Given the high cost of designing ASICs, it is necessary to validate the theoretical diagram resulting from the functional specification as completely as possible in order to eliminate any remaining errors before beginning the preparation of the production file of the ASIC for the foundry. That is why the description level of the model of the ASIC is used for the functional verification of the design of the ASIC prior to starting the technological production process. The purpose of the verification is to verify the compliance of the behavior of the HDL-type model of the ASIC with its functional specification.
With the increasing complexity of ASICs linked to their high degree of integration and the high cost of manufacturing them, the functional verification makes up a prominent part (more than 60%) of the design phase of the circuit, which will tend to increase even more substantially in the years to come.
Hence the need to have a solid functional verification methodology.
It is within this context that one of the advantages of the proposed invention lies.
When samples of the ASIC physical component have been produced, the industrial user validates the functionality of the system consisting of the ASIC physical component and application program executed by the ASIC and verifies that they comply with the specifications of the system. During this phase, the ASICs, mounted in their packages, are connected, on their card, to their real system environment so as to constitute a validation platform.
The proposed invention can also be applied in this phase.
In order to functionally verify the various parts constituting the model of the ASIC, such as the arithmetic unit, memories, counters, combinational logic, router with cache, and other elements, it is possible to activate them separately, insofar as each of them is directly accessible via the simulated input/outputs of the ASIC and sufficiently independent of the others. One then verifies that the part in question conforms to a logical functional model defined in the specifications. It is also necessary to verify the interoperation of the various parts, by simultaneously activating several of these parts. In particular, it is necessary to perform combinational tests between the parts, in order to try to verify the absence of any configurations of states of the various respective parts that were not planned during the design of the functional model, and that could result in defective operation, for example a mutual inhibition between two parts. It is easy to understand that the number of combinational tests increases much faster than the number of circuits or transistors in the ASIC. In addition, the presence of memories in the ASIC that can control some of its circuits results in the fact that the global state of the various outputs, for inputs having the same global state at a given instant, depends on the history of the progression of the previous input states.
The debugging of the programming of functional tests is long and expensive. In practice, this debugging is done using the model of the ASIC. In other words, as soon as the model is designed, it is possible to try to detect the following two types of errors: residual errors in the specifications, and errors or omissions in the programs for the functional validation of the ASIC or in the application programs. This accumulation of tasks, each of which reacts to the others, is obviously difficult to manage, and it entails costs and delays.
The present invention seeks to limit one or more of these disadvantages.